The present disclosure relates to memory testing, and more specifically, to memory testing of three dimensional (3D) stacked memory. Errors in a memory cell of a computing system may be caused by a manufacturing defect, degradation over time, breakage, electrical or magnetic interference, etc. Redundant memory cells may be used to record parity and enable detection of errors. However, parity checking may detect limited types of errors (e.g., single-bit errors), leaving other errors undetected. A suite of test patterns may be developed to detect various types of errors. However, using test patterns may require that the computing system be offline during memory testing. Additionally, when an error is detected in a memory cell of a three-dimensional (3D) stacked memory, the entire stack of memory may have to be replaced with a redundant stack.